SOC Verification using SystemVerilog
A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
What you’ll learn
SOC Verification using SystemVerilog
- Learn the important concepts in SOC/ASIC/VLSI design verification flow
- Learn the System Verilog language for Functional Verification usage
- Be ready and qualified for a Verification job in the semiconductor industry
- Udemy Certification on successful course completion
- Be able to code, simulate and verify SystemVerilog Testbenches
Requirements
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Basic digital design or awareness of chip design flows
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Passion for learning
Description
This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language – which is the most popular Hardware Description Language used for SOC design and verification in the semiconductor industry. The course is organized into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate, and verify using a free browser-based Simulator and Waveform viewer. Quizzes are also added to test the student’s knowledge and progress.
Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course
Who this course is for:
- Students of VLSI, Digital and Embedded System Design, and Microelectronics who wants to be ready for a job in the semiconductor industry
- Digital Design and Verification Professionals who are passionate about continuous learning
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